Parametric Yield Simulator
Circuit Surfer® works in conjunction with a SPICE engine and uses statistical analysis to predict parametric yield as a function of design and process parameters. It is used to set or optimize device sizes in circuits such as memories, RF and analog blocks, critical paths, or in SSTA flows. Circuit Surfer is also used to determine realistic worst-case corners for timing models.
- Use realistic worst-case corners in design - Typical corner modeling is problematic, particularly for analog design. Circuit Surfer® can be used in statistical flows that take advantage of physically meaningful worst-case corners which eliminate physically non-sensible correlations. Using Circuit Surfer® with statistical models, designers and process/modeling engineers can agree on the level of verification (e.g. 3, 4, 5, or 6-sigma) and verify those in simulation based on physically meaningful data.
- Seamless integration into design flows - Circuit Surfer® provides native integration to the Cadence analog design environment, enabling an easy learning curve in a familiar setting.
- Computational efficiency - The Design of Experiments and Response Surface Models implemented in Circuit Surfer® lead to faster run times that achieve more accurate results than simple Monte Carlo approaches.
- Patented mismatch algorithm - Circuit Surfer® employs an efficient method to simulate mismatch with a large number of devices. The software identifies critical devices for mismatch and ranks them for designers.
- Supports patented PDF Solutions PCM methodology - Circuit Surfer® enables product parametric yield loss diagnosis based on PCM production test data, for rapid resolution of parametric yield loss issues in production.
Contact us to discover more about how PDF Solutions can address your critical issues throughout the IC Manufacturing Process Life Cycle.