How PDF Solutions Improves IC Yield, Performance, and Reliability
Built on nearly three decades of research PDF Solutions' proven methods and technologies for Process-Design Integration target substantial yield, performance and reliability improvement. Our Process-Design Integration approach consists of three essential elements:
- Characterization: Comprehensive modeling of process-design interactions to identify the yield limitations for a broad set of fundamental design elements, and the effects of process variations on circuit performance.
- Prioritization: Focus on the most important yield issues based on an analysis of yield-loss components by process module, design block, defect type (random vs. systematic), and contribution to overall product yield.
- Optimization: Simulation and validation of yield, performance, and reliability improvement recommendations.
Our approach provides highly accurate prediction and detailed assessment of yield loss. Our proprietary technology characterizes process and design interactions, extracts the design attributes that impact product yield, and models the yield impact of critical design characteristics and manufacturing steps.
To calibrate the yield models, PDF Solutions designs a full suite of Characterization Vehicle™ (CV™) test chips for IDM and foundry customers. In addition, PDF has developed a full-flow Universal CV™ test chip that pre-characterizes selected foundry process technologies, accelerating the deployment of PDF Solutions' services for foundry users. All PDF CV test chips incorporate a design-of-experiments (DOE) that focuses on design attributes with critical yield risk, such as via configurations (including local and global neighborhood effects), and over-layer and under-layer characteristics.
PDF Solutions' proprietary software uses the data derived from the CV test chips in the target process to analyze and model the influence of design improvements and critical process-modules changes.
PDF Solutions' varied modeling and simulation technologies are used to quantify and understand statistical process-design interactions, including the following:
- Efficient modeling and pattern-recognition algorithms,
- Statistical process and device simulation,
- Statistical simulation of circuit performance,
- Hierarchical layout processing.
As possible layout and process modifications are established, appropriate simulations validate and quantify their yield impact.
PDF Solutions' software-based prioritization techniques make possible a broad yet rapid exploration of potential yield and performance improvements. After simulation and validation of potential improvements, prioritization analysis results in actionable optimization recommendations in:
- the process, making it more amenable to certain designs, and
- the design, making it less sensitive to critical manufacturing steps.
These improvements can be accomplished before the design has been run in the fabrication facilities, and, based on PDF Solutions' business and technical analysis, customers can choose the most cost effective option.
|
| Module |
|
Product B Original Layout |
Product B Extra Via Borders |
Product B Extra Via Borders + Plowed Metal |
| Lambda DO |
Counts/
Ac(p) |
Yield |
Counts/
Ac(p) |
Yield |
Counts/
Ac(p) |
Yield |
| Gate -- all poly |
0.3 |
0.029 |
0.99 |
0.029 |
0.99 |
0.023 |
0.99 |
Metal1 -- shorts
Metal2 -- shorts
Metal3 -- shorts |
0.28
0.78
2 |
0.151
0.170
0.044 |
0.96
0.88
0.92 |
0.151
0.170
0.044 |
0.96
0.88
0.92 |
0.022
0.138
0.036 |
0.97
0.9.
0.93 |
Contact N+Active Area
Contact P+Active Area
Contact to Poly |
8.5
7.6
4.9 |
5.9E+06
3.1E+06
4.9E+06 |
0.95
0.98
0.98 |
5.9E+06
3.1E+06
4.9E+06 |
0.95
0.98
0.98 |
5.9E+06
3.1E+06
4.9E+06 |
0.95
0.98
0.98 |
Via12 -- min border
Via12 -- full border
Via23 -- full border
Via34 -- full border |
30
2.5
1.9
9 |
6.5E+06
2.0E+06
6.0E+04
3.7E+06 |
0.82
0.99
1.00
0.97 |
6.4E+06
2.2E+06
6.0E+04
3.7E+06 |
0.83
0.99
1.00
0.97 |
4.5E+06
4.0E+06
6.0E+04
3.7E+06 |
0.87
0.99
1.00
0.97 |
| Total |
|
|
0.55 |
|
0.55 |
|
0.61 |
| Chips/Wafer |
|
320 |
175 |
320 |
175 |
300 |
182 |
|
Yield Impact Matrix result: a predicted yield of various layout features and the yield impact of via border size
|
