Solutions :: Technology
					Core Technologies of PDF Solutions Process-Design Integration infrastructure PDF's Process-Design Integration approach minimizes all major sources of yield loss. Our proprietary technologies allow us to build highly accurate models of both yield and performance. Since our models start with individual circuit-elements, and we validate each circuit-element's predicted function with custom test chips, we can simulate the effects of specific variations in either design and/or process. Functional and performance yield losses are modeled, with both random and systematic root causes identified. Quantified yield loss mechanisms are then summarized in a deliverable Yield Impact Matrix. PDF's simulation technologies allow for Characterization, Prioritization, and Optimization, and include the following: Characterization Vehicle™ test chips to validate yield and performance models, and for rapid detection of process changes, Simulation of product-level functional yield resulting from specific design attributes and process-modules, Simulation of circuit performance-distribution resulting from process variation, Simulation of device performance resulting from process variation. By working closely with clients, PDF Solutions delivers maximum benefits and optimal value. Our Process-Design Integration solutions provide pre-silicon insight into major yield issues, and dramatically improve time-to-volume production while reducing product costs. TECHNOLOGY AND ENABLING TOOLS Core Technologies Enabling Tools Description Process Characterization Characterization Vehicle™ and Universal CV™ test-chips Patented, comprehensive process characterization test vehicles with DOEs pdFasTest™ hardware system Highly efficient parallel testing of CVs pdCV™ software Layout systematic yield modeling and process margin analysis tailored for CVs; random defect size distribution extraction Functional Yield [Simulation and Modeling] Yield Ramp Simulator™ software Design attribute extraction and feature-based yield modeling; DFM opportunity analysis and post-tapeout layout optimization Parametric Yield [Simulation and Modeling] Circuit Surfer® software Efficient statistical SPICE environment for Analog circuit verification and optimization Process Optimization pdFab® software Statistical TCAD simulation environment Optissimo™ software Optical proximity correction and verification software Product Optimization pDfx™ design platform Process-aware DFM environment, including IP kit and simulation tools Product Manufacturing Yield Monitoring and Response System (YMRS) software Model-driven production monitor for in-line and e-test analysis Shot-map Optimization WAMA™ WAfer MApping software Lithography shot-map optimization to increase good die per wafer Simulation environment allows practical deployment of PDF Solutions' technology, which has been incubated and proven over many integration and yield ramp cycles.