Abstract: Detection and monitoring of the yield loss mechanisms and defects in product chips have been a subject of extensive efforts, resulting in multiple useful Design-for-Manufacturing (DFM) and Design-for-Test (DFT) techniques. Defect inspection techniques extend optical inspection further into sub-10 nm nodes, but many buried defects are formed as a result of multi-layer 3-D interaction, and they are difficult to detect by surface optical scans. In case of a functional failure related to a defect (an open or a short), the localization of the fail site for failure analysis and root cause identification is often difficult, especially for random logic design. In this paper we describe a new -DFM methodology which inserts into the product design special test structures to support New Product Introduction (NPI) and a product yield ramp. The structures are part of PDF Solutions’ proprietary Design-for-Inspection (DFI) system with no penalty to the product layout. They are designed to be electrically tested in a non-contact way using a dedicated and specially optimized e-Beam tool. The layouts of these structures are based on the standard cell design therefore they can be used as filler cells in standard cell-based logic designs. The paper presents the concept of the test structures and their design to cover specific failure modes and enable fail mechanism identification. We describe the design flow to integrate the structures into the product floorplan and the non-contact test methodology to scan product wafers and detect failures. Finally, we demonstrate usage of such DFI structures and provide results collected from scanning product wafers containing embedded DFI filler cells.
Keywords: Design for Manufacturing, Test Structure, E-beam, Defect, Inspection, Characterization, Standard Cells, Yield
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