More Data, More Integration, Same Deadlines
Moderated by Ed Sperling/Semiconductor Engineering
Experts at the Table: Semiconductor Engineering (SE) sat down to discuss the future of chip design and EDA tools with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; and Babak Taheri, CEO of Silvaco. What follows are excerpts of a panel discussion held by the SEMI ESD Alliance.
SE: We’re moving from a world of homogeneous planar designs into one of heterogeneous, multi-die packages. So while some of this may be evolutionary, it’s still a big jump. What does that mean for design and tools and reliability?
Kibarian: When you did a monolithic chip, 95% of the value was the foundry building that chip. Then you’d move to wafer sort, and packaging was an afterthought with 99.99% yield, followed by speed binning and test. The test was at the end of the flow, and it was just a final check. Now, if you look at most chiplet-type strategies, test is in the middle of the flow. There’s a lot of value being added in the packaging and combining of a lot of chips, whether it’s panel integration or reconstituted wafers. The manufacturing flow is a lot more complex, and the risk is on the product groups, not as much on the foundries. There are more sophisticated screening approaches, more data required in the assembly flow as it becomes much more important, and integrating across the supply chain is now a requirement to drive reliability and to get cost and yield to where people expect them to be. It’s now a very mechanical process, whereas in the past it primarily used to be a chemical and physical process.