Publications
- Design Compliant Source Mask Optimization (SMO)
- Estimating_MOSFET_Leakage_from_Low-cost_Low-resolution_Fast_Parametric_Test
- Online Deployment of Robust Metrology Prediction Mode
- BEOL parametric variation control with FDC data
- Enabling PCM Prediction and Control using FDC Data
- High Density Test Structure Array for Accurate Detection and Localization of Soft Fails
- Variation in Transistor Performance and Leakage in Nanometer-Scale Technologies
- Device Array Scribe Characterization Vehicle Test Chip for Ultra Fast Product Wafer Variability Monitoring
- Yield Improvement Using a Fast Product Wafer Level Monitoring System
- Scribe Characterization Vehicle Test Chip for Ultra Fast Product Wafer Yield Monitoring
- Test Structures and Analysis Techniques for Estimation of the Impact of Layout on MOSFET Performance and Variability
- Passive Multiplexer Test Structure For Fast and Accurate Contact and Via Fail-Rate Evaluation
- Test Time Reduction Methods for Yield Test Structures
- Characterization and Modeling of MOSFET Mismatch Of a Deep Submicron Technology
- Logic Characterization Vehicle to Determine Process Variation Impact on Yield and Performance of Digital Circuits
- Fast Extraction of Defect Size Distribution Using a Single Layer Short Flow NEST Structure
- Predictive Yield Modeling of VLSIC’s
- Circuit-Device Co-design for High Performance Mixed-Signal Technologies
- A New Defect Distribution Metrology with a Consistent Discrete Exponential Formula and Its Applications
- Impact of Unrealistic Worst Case Modeling on the Performance of VLSI Circuits in Deep Sub-Micron CMOS Technologies
- A New Methodology for Concurrent Technology Development and Cell Library Optimization
- Predictive Yield Modeling for Reconfigurable Memory Circuits
- Advanced Yield Learning Through Predictive Micro-Yield Modeling
- A Pattern Matching Algorithm for Verification and Analysis of Very Large IC Layouts
- Chip Scale 3-D Topography Synthesis
- Analysis of the Impact of Process Variations on Clock Skew
- Yield Learning Through Design Attribute Extraction
- WAMATM - A Method of Optimizing Reticle/Die Placement to Increase Litho Cell Productivity
- Statistical SPICE Model Characterization
- Simulating the Impact of Poly-CD Wafer-Level and Die-Level Variation on Circuit Performance
- Simplify to Survive, Prescriptive Layouts Ensure Profitable Scaling to 32nm and Beyond
- Robust Mesh Generation for Fast, Accurate and Stable TCAD
- Realistic Worst-Case Modeling by Performance Level Principal Component Analysis
- OPC Simplification and Mask Cost Reduction Using Regular Design Fabrics
- Old Rules No Longer Apply
- New Methodology for Ultra-Fast Detection and Reduction of Non-Visual Defects at the 90nm Node and Below Using Comprehensive E-Test Structure Infrastructure and Inline Dualbeam™ FIB
- Modeling of Substrate Noise Injected by Digital Libraries
- Method for Fast and Accurate Calibration of Litho Simulator for Hot Spot Analysis
- Maximization of layout printability/manufacturability by extreme layout regularity
- Holistic Yield Improvement™: A Comprehensive Methodology for Accelerated Yield and Performance Ramping
- Holistic Yield Improvement Methodology
- Guide to Achieving World-Class Semiconductor Manufacturing Results
- Fast Characterization of Electrical Fails Overlaying to Inline Defect Inspection During 90 Nm Copper Logic Technology Development
- Failure Mode Detection and Process Optimization for 65 Nm CMOS Technology
- Enabling Technology Scaling with “In Production” Lithography Processes
- Elimination of Meshing Noise in Statistical TCAD
- Conquering Process Variability: A Key Enabler for Profitable Manufacturing in Advanced Technology Nodes
- An Asymptotically Constant, Linearly Bounded Methodology for the Statistical Simulation of Analog Circuits Including Component Mismatch Effects
- Active Voltage Contrast and Seebeck Effect Imaging as Complementary Techniques for Localization of Resistive Interconnections
- Accelerated 65nm Yield Ramp Through Optimization of Inspection on Process-Design Sensitive Test Chips
- A Novel Methodology for Reducing the Flash Memory Development Cycle
- A Methodology for Modeling the Effects of Systematic Within-Die Interconnect and Device Variation on Circuit Performance
- A High Performance 0.18μm BiCMOS Technology Employing High Carbon Content in the Base Layer of the SiGe HBT to Achieve Low Variability of hFE
- 65nm Yield Detractor Caused by M1 Filament Shorts and Solution
