As semiconductor scaling continues to push toward smaller nodes, understanding the subtle effects of patterning variations has become critical for optimizing device performance. A recent IEEE paper by researchers from PDF Solutions and the University of Brescia* reveals how seemingly minor changes in gate and fin spacing can significantly impact transistor performance through mechanical stress modulation; with drive current variations reaching up to 13% in 7nm FinFET technology.
The Challenge: Patterning Variability Meets Stress Engineering
Modern FinFET devices rely heavily on mechanical stress to boost performance.
PMOS transistors use SiGe source/drain regions to introduce compressive stress that enhances hole mobility, while NMOS devices may benefit from tensile strain components introduced by the overall process and device architecture.
However, advanced patterning techniques like Self-Aligned Double Patterning (SADP) for gates and Self-Aligned Quadruple Patterning (SAQP) for fins, while excellent at controlling critical dimensions, introduce variability in the spacing between features.
This spacing variability directly affects the volume and morphology of epitaxially grown source/drain regions, which in turn modulates channel stress and ultimately impacts carrier mobility and drive current.
Key Findings: Poly Pitch Effects
The research team designed specialized test structures with systematic variations in both poly pitch (±7%) and fin pitch (±10%) to isolate and quantify these effects.
PMOS devices showed the most straightforward response to poly spacing changes:
- Drive current varied linearly from -11% to +7% across the tested range
- Wider poly spacing increases the SiGe stressor volume, enhancing longitudinal compressive stress
- The dominant mechanism is stress-enhanced hole mobility in the channel
NMOS devices exhibited a more complex, sublinear behavior:
- Performance changes ranged from -13% to +5%
- The effect stems primarily from tungsten contact fill rather than epitaxial growth
- Vertical and longitudinal stress components partially offset each other
Importantly, the team used rigorous Y-Function de-embedding analysis to confirm that while parasitic resistance changes significantly with spacing (up to +30% for PMOS), the dominant driver of performance variation is intrinsic channel mobility modulation, not parasitic effects.
Fin Pitch Impact: Smaller but Still Significant
Fin pitch variations produced more modest but still measurable effects:
- NMOS: ±2% current variation for ±7% fin pitch changes
- PMOS: ±1% variation for the same pitch range
The smaller impact on PMOS devices is somewhat counterintuitive given their use of SiGe stressors. The explanation lies in competing stress components: as fin spacing increases, beneficial vertical stress improvements are offset by reductions in longitudinal stress.
The Pitch Walking Problem
An intriguing complication arises from the SAQP patterning process itself. Mandrel CD variations create a phenomenon called “pitch walking,” where spacing between adjacent fins varies while the total four-pitch width remains constant. This affects 4-fin devices differently depending on their alignment within the fin array, creating three distinct sensitivity patterns that designers must account for.
TCAD Validation and Physical Mechanisms
The study’s strength lies in its combination of silicon measurements with comprehensive 3D TCAD simulations using Synopsys Sentaurus. The simulations included:
- Lattice Kinetic Monte Carlo modeling of epitaxial growth
- Thermo-mechanical stress calculations accounting for lattice mismatch
- Thermal expansion effects from tungsten contact deposition
- Stress-dependent mobility modeling
The excellent agreement between simulation and measurement validates the physical understanding and provides a predictive framework for design optimization.
Implications for Design and Manufacturing
These findings have several practical implications:
- Tight pitch control is essential: The 13% performance swings observed with poly spacing variations can significantly impact product performance, making tight process control critical.
- Layout-dependent effects must be modeled: Standard cell libraries and design tools need to account for these stress-related layout dependencies.
- Device placement matters: In 4-fin devices, alignment relative to SAQP mandrels creates placement-dependent sensitivities that impact matching and variability.
- Different sensitivities by device type: PMOS shows greater sensitivity to poly pitch, while NMOS is more affected by fin pitch—designers can use this knowledge strategically.
Looking Ahead: Gate-All-Around Considerations
While this work focuses on bulk FinFETs, the authors note that the methodology should extend to next-generation Gate-All-Around (GAA) nanosheet transistors, though extensive recalibration will be needed. GAA’s fundamentally different structure—with released nanosheets rather than continuous fins—creates more complex strain coupling mechanisms and different stress propagation paths.
Conclusion
This comprehensive study demonstrates that mechanical stress modulation remains a critical—and sometimes underappreciated—factor in advanced CMOS performance. As the industry continues scaling, understanding and controlling these layout-induced stress effects becomes increasingly important for meeting performance targets and minimizing variability.
For process engineers, the message is clear: poly-to-poly spacing control deserves the same attention as critical dimension control. For designers: layout matters more than ever, and stress-aware design practices are no longer optional at advanced nodes.
*The full study, “Impact of the Gate and Fin Space Variation on Stress Modulation and FinFET Transistor Performance” by Angelo Rossoni, Tomasz Brozek, and Zsolt M. Kovacs-Vajna, was published in IEEE Transactions on Electron Devices