Abstract: Device scaling in advanced CMOS nodes is becoming more difficult due to patterning limitations and complex 3-D transistor integration schemes. This also makes the devices more sensitive to patterning variability. The presented study investigates the impact of poly pitch and fin pitch variability on stress-induced performance variation in 7nm FinFET transistors. Variations in critical dimension (CD) during patterning can alter fin width and spacing, leading to changes in device characteristics. We evaluated device sensitivity using a comprehensive set of test structures and performed TCAD simulations to model the effects. The results confirm that both NMOS and PMOS devices are sensitive to poly spacing, NMOS devices exhibit up to a 13% degradation in drive current, whereas PMOS devices show -11% to +7% variation in drive current, and inter-fin spacing. The dominant mechanism behind these effects is stress modulation, particularly due to changes in the volume and shape of epitaxially grown source/drain regions. These findings highlight the critical role of mechanical stress in FinFET performance and underscore the importance of pitch control to minimize variability and optimize device parametric targets.
Keywords: FinFET, 7nm technology, TCAD, Poly pitch, Fin pitch, Mechanical stress, Transistor performance
Fill out the form below to download the paper:
By downloading this information I agree that PDF Solutions, Inc. may use my information provided herein to contact me about its products and services, even if I have previously unsubscribed from such communications. For information on our privacy practices and commitment to protecting your privacy, please review our Privacy Policy.